1. Field of the Invention
The present invention relates to a logic circuit which is formed by combination of bipolar transistors and CMOS transistors.
2. Description of the Prior Art
As is generally known, there are many logic circuits formed by combining bipolar transistors and CMOS transistors. FIG. 4 shows an inverter circuit as such a well-known logic circuit which is disclosed in Japanese Patent Laying-Open Gazette No. 11034/1984. Referring to FIG. 4, a PMOS transistor T.sub.1 has a gate connected with an input terminal IN, a source connected with a high-potential power source 1 and a drain connected with an end of a first resistor R.sub.1. Another end of the first resistor R.sub.1 is connected to an output terminal OUT. An NMOS transistor T.sub.2 has a gate connected with the input terminal IN, a drain connected with the output terminal OUT and a source connected with an end of a second resistor R.sub.2 . Another end of the second resistor R.sub.2 is connected to a low-potential power source 2 of the ground level. A first NPN transistor T.sub.3 is provided for charging an output load C and a second NPN transistor T.sub.4 is provided for discharging the output load C. The first NPN transistor T.sub.3 has a base connected to the drain of the PMOS transistor T.sub.1, a collector connected to the high-potential power source 1 and an emitter connected to the output terminal OUT. The second NPN transistor T.sub.4 has a base connected to the source of the NMOS transistor T.sub.2, a collector connected to the output terminal OUT and an emitter connected to the low-potential power source 2. The output load C is not provided as an actural element, but expressed as the total sum of output capacity parasitic to the inverter itself and input capacity of a gate connected to a subsequent stage of the inverter.
When input voltage V.sub.IN of a low level (GND level) is applied to the input terminal IN in the aforementioned circuit, the NMOS transistor T.sub.2 and the NPN transistor T.sub.4 are turned off while the PMOS transistor T.sub.1 is turned on. Since the PMOS transistor T.sub.1 is thus turned on, the high-potential power source 1 supplies current to the base of the NPN transistor T.sub.3 and the first resistor R.sub.1, to turn on the NPN transistor T.sub.3. Thus, the output load C between the output terminal OUT and the low-potential power source 2 is charged.
Assuming that V.sub.DD represents source voltage of the high-potential power source 1 and V.sub.BE(T3) represents forward voltage of the NPN transistor T.sub.3 in the aforementioned process of charging the output load C, charging of the output load C is mainly performed through a current flow path by the NPN transistor T.sub.3 in an interval T.sub.OUT1 as shown in FIG. 5 in which the potential of the output terminal OUT, i.e., output voltage V.sub.OUT is: EQU V.sub.OUT &lt;V.sub.DD -V.sub.BE(T3) ( 1)
When the current voltage V.sub.OUT becomes: EQU V.sub.OUT .gtoreq.V.sub.DD -V.sub.BE(T3) ( 2)
in an interval T.sub.OUT2 as shown in FIG. 5, the NPN transistor T.sub.3 is turned off and the output load C is charged through a path of the PMOS transistor T.sub.1 and the resistor R.sub.1. Thus, the output voltage V.sub.OUT is finally raised up to V.sub.DD.
Then, when input voltage V.sub.IN of a high level (V.sub.DD) is applied to the input terminal IN, the PMOS transistor T.sub.1 and the NPN transistor T.sub.3 are turned off while the NMOS transistor T.sub.2 is turned on. Since the NMOB transistor T.sub.2 is thus turned on, charges in the output load C flow to the base of the NPN transistor T.sub.4 and the second resistor R.sub.2 through the NMOS transistor T.sub.2. Thus, the NPN transistor T.sub.4 is turned on to rapidly discharge the output load C.
Assuming that V.sub.BE(T4) represents forward voltage of the NPN transistor T.sub.4 in the aforementioned process of discharging the output load C, discharging is performed mainly through a current flow path by the NPN transistor T.sub.4 in an interval T.sub.IN1 as shown in FIG. 5, in which the output V.sub.OUT is: EQU V.sub.OUT .gtoreq.V.sub.BE(T4) ( 3)
When the output voltage V.sub.OUT becomes: EQU V.sub.OUT &lt;V.sub.BE(T4) ( 4)
in an interval T.sub.IN2 as shown in FIG. 5, the NPN transistor T.sub.4 is turned off and discharging is performed through a path of the NMOS transistor T.sub.2 and the resistor R.sub.2. Thus, the output voltage V.sub.OUT is finally lowered to the GND level.
As obvious from the above description, the waveform in rise time of the output voltage V.sub.OUT is substantially determined by the value of resistance of the PMOS transistor T.sub.1 in ON-state and the time constant on the basis of the resistance R.sub.1 and the capacity of the output load C in a range of V.sub.OUT .gtoreq.V.sub.DD -V.sub.BE(T3) in this inverter circuit. Further, the waveform in fall time of the output voltage V.sub.OUT is substantially determined by the value of resistance of the NMOS transistor T.sub.2 in ON-state and the time constant on the basis of the resistance R.sub.2 and the capacity of the output load C in a range of V.sub.OUT .ltoreq.V.sub.BE(T4).
In the conventional logic circuit as hereinabove described, it takes time for the output voltage V.sub.OUT to reach the V.sub.DD level or the GND level in the rise or fall time. When the input voltage V.sub.IN is increased in frequency, therefore, the input voltage V.sub.IN may be changed before the output voltage V.sub.OUT reaches the GND or V.sub.DD level as shown in FIG. 6 whereby no sufficient output amplitude can be obtained with respect to input amplitude. Thus, if the same logic circuits are connected with each other in multiple stages, for example, decrease in input amplitude to a subsequent stage causes reduction in noise margin in the subsequent stage as shown by symbol A in FIG. 6, or increase in current flowing between the high-potential power source 1 and the low-potential power source 2 through the transistors T.sub.1 and T.sub.2 in the subsequent stage.
In order to avoid this, it may be considered to reduce values of the resistances R.sub.1 and R.sub.2 while increasing current flow capacity of the PMOS transistor T.sub.1 and the NMOS transistor T.sub.2. However, such means leads to increase in current flowing between the high-potential power source 1 and the low-potential power source 2 through the transistors T.sub.1 and T.sub.2 in operation of the logic circuit as well as to increase in transistor area, whereby an integrated circuit formed through the logic circuit is increased in power consumption and chip area.